1. Field of the Invention
The present invention relates to logic amplifiers, and in particular, to logic amplifiers which receive and convert nondifferential logic signals to differential logic signals.
2. Description of the Related Art
As the number of different types of digital logic families and signals has grown, so has the need for logic amplifiers, or translators, for converting one type of logic signal to another. A good example of such a circuit is a logic amplifier which receives a nondifferential logic signal, such as one compatible with complementary metal oxide semiconductor ("CMOS") technology, and converts it to a differential logic signal compatible with common mode logic ("CML"), such as emitter-coupled logic ("ECL"). Such a circuit must receive and translate the CMOS signal (which has a signal amplitude swing between the power supply potential VDD and ground GND) to an ECL or CML signal (which has a signal amplitude swing of 800 millivolts ["mv"] or 400 mv, respectively).
Referring to FIG. 1, a conventional logic amplifier 10 for performing this function is shown. This amplifier 10 is biased between a positive voltage supply VDD and the circuit reference, i.e. ground GND, and includes an input amplifier 12, current source 14, biasing circuit 16 and output amplifier 18. As shown, the input amplifier 12 consists of two source-coupled metal oxide semiconductor field effect transistors ("MOSFETs") M1 and M2 whose drain terminals are tied to VDD by resistors R1 and R2, respectively. The current source 14, consisting of NPN bipolar junction transistor ("BJT") Q1 and resistor R3 biased by a fixed biasing voltage VB, provides a bias current for the input amplifier 12. (The fixed biasing voltage VB is typically provided by a reference voltage generating circuit called a "bandgap" circuit [not shown] which is powered by the main power supply VDD.) The biasing circuit 16 produces a fixed biasing voltage VA according to voltage dividing resistors R6 and R7. (The biasing voltage VA is typically fixed at VDD/2, e.g. 2.5 volts for VDD=5 volts.) Output amplifier 18 consists of transistor pairs Q4/Q2 and Q5/Q3 which are each coupled in a totem-pole configuration (along with resistors R4 and R5, respectively) and biased by a fixed biasing voltage VD. Parameters and component values for this circuit 10 are summarized below in Table 1.
TABLE 1 ______________________________________ FIGS. 1-4 ______________________________________ VDD 3.0 volts dc VB 1.2 volts dc M1 N-MOSFET M2 N-MOSFET Q1 NPN Bipolar Q2 NPN Bipolar Q3 NPN Bipolar Q4 NPN Bipolar Q5 NPN Bipolar Q6 (FIG. 2) NPN Bipolar R1 20 K.OMEGA. R2 20 K.OMEGA. R3 20 K.OMEGA. R4 30 K.OMEGA. R5 30 K.OMEGA. R6 10 K.OMEGA. (FIG. 1) 100 K.OMEGA. (FIG. 2) R7 10 K.OMEGA. (FIG. 1) 20 K.OMEGA. (FIG. 2) I1 Bias Circuit (FIGS. 3, 3A) C-MOSFET Inverter (FIG. 4) ______________________________________
The MOSFET M1 receives a single-ended, i.e. nondifferential, CMOS-compatible input signal VIN while MOSFET M2 receives a fixed biased voltage VA established by the voltage divider biasing circuit 16 of resistors R6 and R7. The result of these two inputs VIN and VA produce a differential output voltage VD across the drain terminals of MOSFETs M1 and M2. The output amplifier 18 receives this differential signal VD and converts it to two nondifferential output signals VOUT and VOUT* which together form the two phases of a differential output signal VOUT-VOUT* (where "X*" indicates a signal which is the inverse phase, i.e. .+-.180.degree. [approx.], of signal "X").
Referring to FIG. 2, an alternative circuit 20 also includes the input amplifier 12, current source 14 and output amplifier 18, as discussed above. However, the biasing circuit 26 is different in that BJT Q6, biased by the biasing voltage VB, is used to generate the biasing voltage VA (e.g. as an active biasing voltage rather than as the passive biasing voltage generated by the passive biasing circuit 16 of FIG. 1). (Parameters and component values for this circuit 20 are summarized above in Table 1.)
Referring to FIG. 3, a further alternative circuit 30 also includes the input amplifier 12, current source 14 and output amplifier 18, as discussed above. However, yet another form of biasing circuit 36 is used for generating the biasing voltage VA. Inverter I1, with its input and output terminals connected together produce the biasing voltage VA. This type of active voltage divider biasing circuit 36 is well known in the art and is shown in FIG. 3A. Complementary MOSFETs MP and MN, with their source terminals connected to VDD and ground GND, respectively, and their gate and drain terminals all connected together, produce an active biasing voltage VA since both MOSFETs MP and MN are biased on and thereby effectively operate as a voltage divider between VDD and ground. As is known in the art, the actual DC voltage potential available at the output VA can be preselected by appropriately scaling the device geometries (e.g. the channel widths and lengths) of the two MOSFETs MP and MN. (Parameters and component values for this circuit 30 are summarized above in Table 1.)
These conventional circuits 10, 20, 30 have a number of disadvantages. One problem involves the amount of static power consumption in the biasing circuits 16, 26, 36 (due to the static current drain through resistors R6 and R7 [FIGS. 1 and 2] and MOSFETs MP and MN [FIG. 3A]). Another problem involves biasing problems encountered when the circuits 10, 20, 30 are operated at a low power supply voltage VDD. This problem arises when VDD falls below 3.0 volts. At such a low biasing voltage, the biasing voltage VA falls to where it may become too close in value to the dc potential VCQ1 at the collector of BJT Q1. With VB fixed (e.g. due to the relative insensitivity of the bandgap circuit to VDD) and VA falling with the lower VDD, the voltage difference VA-VCQ1 between them may not be sufficient to ensure that (1) MOSFET M2 is turned on when appropriate and (2) BJT Q1 stays out of saturation. (At a minimum, this difference VA-VCQ1 must be equal to or greater than the sum of the threshold V(TH) and saturation VDS(SAT) voltages for MOSFET M2 [e.g. 0.7+0.2=0.9].)
Referring to FIG. 4, another conventional circuit 40 has been implemented as an attempt to overcome the above-mentioned problem of static power consumption in the biasing circuits 16, 26, 36. In this circuit 40, no biasing circuit is used. Rather, the input signal VIN is fed directly to the gate of MOSFET M1, as before, and also to an inverter I1 so as to feed the inverse VIN* of the input signal VIN to the gate of MOSFET M2. In other words, the input amplifier 12 is now operated as a differential amplifier in that its input signals VIN and VIN* form the two signal phases of a differential input signal VIN-VIN*. (Parameters and component values for this circuit 40 are summarized above in Table 1.)
Ideally, the two input signals VIN and VIN* should be exactly out of phase and thereby cause MOSFETs M1 and M2 to alternate in their conductance of the biasing current IQ1 provided by the current source 14. In other words, the MOSFET currents IM1 and IM2 should ideally be exactly out of phase with one another and should each equal the biasing current IQ1. However, referring to FIG. 5A, such is not the case. The invertor I1, when inverting the input signal VIN to produce its inverse VIN*, introduces a slight time delay t(I1), or phase lag. Thus, the corresponding leading and trailing edges of the inverse phase VIN* lag those of the input phase VIN by this delay time t(I1).
Accordingly, the output signal currents IM1 and IM2 are also out of phase by t(I1). This means that for this brief period of time t(I1), during each high-to-low logic transition of the input VIN, neither MOSFET M1 nor M2 are conductive and neither output signal current IM1 nor output signal current IM2 flow within the input amplifier 12. Therefore, no current IQ1 is drawn from the current source 14 and BJT Q1 becomes saturated. This causes a perturbation in the voltage VC at the collector of BJT Q1. In turn, this introduces a noise spike into the biasing voltage VB, which can also affect the output amplifier 18 via BJTs Q2 and Q3. Referring to FIG. 5B, the effects of this phase delay t(I1) on the various signals or voltages VIN, VIN*, VOUT, VOUT* and VC can be better understood.
Therefore, it would be desirable to have a logic amplifier circuit which, while minimizing static power consumption, avoided introducing noise spikes into its bias lines or neighboring circuitry.